1. Field of the Invention
The present invention relates to architecture for a router. More particularly, the present invention relates to architecture for a router with scalable processing power.
2. The Prior Art
Computers generate and utilize large amounts of data. Different components in a computer network, for example, several different computers each with an internet connection or “uplink”, need to be linked together to allow for the transfer of data among the different components in the network. Routers perform this function. Routers take data input from one component in a network and ensure that it is properly transferred to another component in the network.
Different components in a computer network may also generate data in different forms and at different speeds. A router system in conjunction with other network interface components can properly bundle different types of information, transmit the information among different components in a computer network, and ensure that each component of the computer network is allowed to give and receive data at a rate proper for that particular component. Examples of network interface components include Ethernet transceivers and CT3 HDLC channel link data managers (as embodied in the PMC-Sierra CT3 interface chip).
Data bytes are generally bundled into “packets”, a discrete grouping of information bytes that will be transferred together along the router system. Packets containing related information in a logical order are grouped into “flows”. A flow consists of a unidirectional stream of packets to be transmitted between a particular source and a particular destination. Packets within the same flow will have the same source/destination address, the same source/destination port, and the same protocol. It is required to maintain the packet ordering within a flow.
Speed and accuracy are two important features of routers. If the data transfer rate, or throughput rate, is not rapid enough, the end user of the required data must wait for it to arrive, wasting valuable processing time. Also, input and output queues waiting to transfer data may overflow if information is being added more rapidly than it is being removed. Accuracy in transfer is also important to ensure that data arrives at its proper destination in the proper order.
Routers can also provide services as they perform the data transfer or switching. Some of these services involve gathering information about the data being transferred or performing some other processing function upon the data as it is being transferred from one component in the computer network to another. Some of the more recent service developments involve “touching”, or performing some processing function, on the data in most or every packet as it is transferred. Such “high touch” services can require the router system to have a great deal of processing power. New services are being developed all the time, and thus the amount of processing that performing services requires is unbounded.
Current routing systems generally operate on a “one processor per line card” model. A line card is a group of components in a computer network such as a group of modems or an internet connection which sends and receives data. In a “one processor per line card” model, all of the processing for a single line, or a group of related lines, is done by a dedicated processor. This model works acceptably well if the line's rate of data input, or input interface rate, is low enough so that the processor does not become a bottleneck in the system. With low enough interface rates, one processor can handle multiple lines.
However, the line's interface rate may increase as higher-speed computers or internet connections are added. Furthermore, additional router services may become desirable. Eventually, the dedicated processor may no longer be able to keep up with the processing requirements of the line and the throughput rate will slow down. If the throughput rate becomes unacceptably slow, the only solution is generally to replace the dedicated processor with a more powerful machine. This is an expensive solution. In certain cases, for example a high-speed internet line or “uplink”, a processor may not even be available that can keep up with the interface rate of the high-speed line. Current internet uplink rates such as Gigabit Ethernet (1 gigabit per second) are already becoming difficult to handle with a single dedicated processor.
Accordingly, it would be desirable to provide a router architecture that would be easily scalable to accommodate future router service growth as well as expandable uplink connections, and which would allow processors to be added as more processing power became necessary, without requiring the entire system's future hardware needs to be purchased initially. It would also be advantageous to maintain packet ordering within each flow while still flexibly routing among different processors as necessary.